1. Technical Field of the Invention
The invention relates generally to communication systems; and, more particularly, it relates to PLL (Phase Locked Loop) devices within such communication systems.
2. Description of Related Art
PLLs (Phase Locked Loops) are implemented within a wide variety of applications. Most generally, PLLs are employed to lock a frequency of a locally generated signal onto an incoming signal. This functionality may be important in a wide variety of contexts. For example, within data communication receivers (or transceivers), a locally generated signal is typically employed in some way such that the locally generated signal must be synchronized with a received signal that may be received via a communication channel or even simply via a bus (or other interconnection) that interconnects 2 or more devices.
FIG. 1 is a diagram illustrating a prior art PLL (Phase Locked Loop). The operation of a prior art PLL may be described as follows. The prior art PLL receives an incoming signal (shown as coming from a reference oscillator 110) and locks onto it and provides an output signal that is in phase with the incoming signal (e.g., the input signal). The prior art PLL includes a phase detector 120 (having conversion gain Kφ, in Volts/radian), an LPF (Low Pass filter) 130 (sometimes referred to as a loop filter) that limits the frequency spectrum over which the signal is employed, a VCO (Voltage Controlled Oscillator) 140 (having voltage conversion constant KV in radian/S/Volt) that generates a local signal (shown as an output signal having a frequency of
            ω      n        =                                        K            ϕ                    ⁢                      K            V                                    N          ⁢                                          ⁢          R          ⁢                                          ⁢          C                      ,in radian/S) that corresponds to the incoming signal. In this embodiment, R (in Ohms) and C (in Farads) correspond to the values of the resistance and the capacitance of the resistor of the passive LPF 130 illustrated. The output of the VCO 140 is also provided to a divider 150 (that may be a divide by N counter), and the output of the divider 150 is a feedback signal that is used to adjust the phase detector 120 such that the frequency of the signal output from the VCO 140 is a multiple (by a factor of N) of the incoming signal.
The phase detector 120 of the prior art PLL detects the phase difference between the incoming signal to the PLL and the local signal generated by the VCO 140.
In general, a prior art PLL is an electronic circuit that synchronizes the signal from an oscillator (e.g., from the VCO 140) with a second input signal (called the “reference” or “incoming signal”), so that they operate at the same frequency, or multiples of the same frequency.
The loop synchronizes the VCO 140 to the input reference by comparing their phases and controls the VCO 140 in such a manner that a constant phase relationship is maintained between the two signals. If it is determined that the incoming signal and the local signal are in phase (e.g., the two clocks are in phase), then no phase adjustment need be performed. However, if the regenerated clock from VCO 140 lags the reference signal, then the phase adjuster needs to compensate for this by advancing the regenerated clock. If it leads the reference signal, the phase adjuster needs to make the opposite change.
From certain perspectives, PLL circuits are implemented and used for frequency control. They may be configured as frequency multipliers, demodulators, tracking generators or clock recovery circuits. A PLL is basically a feedback control system that controls the phase of the VCO 140. The input signal to the PLL is applied to one input of the phase detector 120. The other input to the phase detector 120 of the PLL is connected to the output of a divider 150 (that may be a divide by N counter) whose input is the output of the VCO 140. Normally the frequencies of both of these signals are nearly the same. The output of the phase detector 120 is pulse width proportional to the phase difference between these two inputs, and this output is applied to a loop filter that is shown as being an LPF (Low Pass Filter) 130 here. It is the combination of the VCO gain, the phase detector gain, the LPF loop filter value (e.g., the loop filter value), and the divider value that determines the dynamic characteristics of the PLL. The filtered signal controls the VCO 140. It is also noted that the output of the VCO 140 is at a frequency that is N times the signal supplied to the frequency reference input. This output signal is sent back to the phase detector 120 via the divider 150 (which may be a divide by N counter).
For additional understanding of the operation of the PLL, it is noted that the loop filter (shown here as the LPF 130) will be designed to match the characteristics required by the application of the PLL. For example, if the PLL is to acquire and track a signal, then the bandwidth of the loop filter will be greater than if it expects a fixed input frequency. The frequency range over which the PLL may lock onto is called the capture range. Once the PLL is locked, the range of frequencies that the PLL follows is called the tracking range. Generally the tracking range is larger than the capture range. The loop filter also determines how fast the signal frequency can change and still maintain lock. This is the maximum slewing rate. The narrower the loop filter bandwidth (or the lower the frequency range of the LPF 130), then the smaller the achievable phase error. This comes at the expense of slower response and reduced capture range.
Typically, the PLL is powered by a power supply that energizes the phase detector 120 and the VCO 140. In some embodiments, where the loop filter is implemented as an active device (e.g., NOT as the passive LPF 130 device as illustrated in this diagram), the power supply may also energize the active components contained therein. The power supply may be located on-chip with, or off-chip from, the PLL.
In some instances, a PLL is implemented to be triggered not off a received clock type signal (having a relatively constant periodicity, duty cycle, amplitude, frequency, and so on), but off of an incoming data signal (whose parameters may vary significantly over time). Such PLLs may generally be referred to as data recovery PLLs. These prior art data recovery PLLs are typically implemented using intelligent phase comparators that make updates only in the presence of data edge transitions. However, it can be very difficult to use a data signal as the reference signal (or incoming signal) to trigger a PLL.
From even a most general consideration, the density of data edge transitions of a digital data signal may be very varied. While the data edge transition density of a typical data signal may in fact be close to 50% (0.5 where a data edge transition occurs every 2 clock cycles) over a relatively long period of time, the data edge transition density within a more localized period of time may vary anywhere from 0% to 100%. That is to say, the number of data edge transitions that occur every period of time may vary from a value of up to 1.0 (e.g., a data edge transition every clock cycle) to a value of down to 0.0 (e.g., no data edge transitions at all within the period of time). When considering a relatively shorter period of time, the data edge transition density statistically is not close to the ideal of 50%. In addition, the PLL loop bandwidth varies as a function of the data edge transition density. That is to say, the loop bandwidth of the PLL is in fact dependent on the data edge transition density. When the data edge transition density is closer to 1, the PLL experiences the widest loop bandwidth because the loop gain is at the highest value. However, when the data edge transition density is closer to 0, the PLL experiences the most narrow loop bandwidth because the loop gain is at the lowest value. An additional loop parameter that varies with transition density is the damping/peaking and hence, the stability thereof. Stabilizing the damping factor generally increases the loop's stability.
In such instances, it can be seen that the local signal (shown as an output signal having a frequency of
            ω      n        =                                        K            ϕ                    ⁢                      K            V                                    N          ⁢                                          ⁢          R          ⁢                                          ⁢          C                      ,in radian/S) will vary as a function of the inverse of the square root of the factor N (e.g.,
                    ω        n            =                                                  1              N                                ·                                                                      K                  ϕ                                ⁢                                  K                  V                                                            R                ⁢                                                                  ⁢                C                                                    =                                                            1                N                                      ·            constant                    ⁢                                          ⁢          value                      )    .
In high performance systems, these variations in loop bandwidth may generate a great deal of deleterious effects. For example, in SONET (Synchronous Optical NETwork, a standard for optical telecommunications transport formulated by the ECSA (Exchange Carriers Standards Association) for the ANSI (American National Standards Institute)), the loop bandwidth is to maintained at less than 8 MHz (Mega-Hertz) and the damping factor is maintained large enough such that the PLL exhibits less than 0.1 dB of jitter transfer peaking. This loop bandwidth requirement inherently puts a significant constraint on the jitter of a VCO that may be implemented in such a PLL. In this SONET example, if the loop bandwidth varies, then the nominal loop bandwidth of the PLL must be placed lower then 8 MHz in an effort to compensate for those instances where the loop bandwidth may expand (based on changes in the data edge transition density). This also requires an even better VCO to meet the jitter specifications within the PLL.
As such, it can be seen that there are many limitations existent within the prior art of data recovery PLLs. A more robust and reliable approach is needed in the art to allow for high performance of data recovery PLLs in view of the variations in data edge transition density that may occur within the data signal by which such a PLL is triggered.